Algorithm/Architecture Co-exploration for Designing Energy Efficient Wireless Channel Estimator

Authors: Meng, Yan; Gong, Wenrui; Kastner, Ryan; Sherwood, Timothy

Source: Journal of Low Power Electronics, Volume 1, Number 3, December 2005 , pp. 238-248(11)

Publisher: American Scientific Publishers

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Abstract:

Wireless networks are making the vision of ubiquitous computing a reality: users will be able to connect anytime and anywhere from anything. To achieve this vision, the next generation of wireless devices must learn about, and adapt to, the transmission environment through a process called channel estimation. In this paper, we describe a cross-cutting approach to explore the design space to solve the channel estimation problem on reconfigurable devices. In particular we focus on the matching pursuit algorithm, which is a fast and accurate iterative algorithm for multipath channel estimation. Our methodology models modern reconfigurable devices as an array of Block RAM-level operation blocks ("BLOBs"), which act as flexible data paths. With the model, we describe design techniques and tradeoffs, resulting in novel optimizations at every level in building an energy efficient MP core, from the theory and algorithms to the bit level. We present results from our design space exploration over a number of different parameters, including both high level characteristics of the application, data and computation partitioning schemes, and module- and bit-level low-power techniques. The results demonstrate the effectiveness and efficiency of our approach to building a high speed and low power channel estimator. The total power saving is 25.4%. We further show that the local, distributed computation is, on average, 145% faster with minimum cost in power dissipation, than the global, centralized computation.

Keywords: LOW ENERGY; CHANNEL ESTIMATION; RECONFIGURABLE ARCHITECTURES; DESIGN METHODOLOGY; REGISTER TRANSFER LEVEL IMPLEMENTATION

Document Type: Research article

DOI: 10.1166/jolpe.2005.049

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