Low Power Test Generation for Path Delay Faults

Authors: Kumar, M. M. Vaseekar; Tragoudas, S.

Source: Journal of Low Power Electronics, Volume 1, Number 2, August 2005 , pp. 194-205(12)

Publisher: American Scientific Publishers

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Abstract:

We propose an implicit test pattern generation method for path delay faults that guarantees high fault coverage such that the power dissipated by the generated test pair of patterns satisfy a given threshold. A timed mixed-mode ATPG that combines function-based and structural (PODEM-like) methods is used for faster and accurate test generation. The power dissipated due to the switching between successive pairs of patterns, is also reduced by incorporating stability functions in the mixed-mode ATPG. Typical delay values are considered from an accurate gate delay model. Data structures like Binary Decision Diagrams and Zero Suppressed Binary Decision Diagrams are used to store and manipulate the test functions and path delay faults respectively. The strength of the proposed method is demonstrated experimentally using some sample benchmark circuits.

Keywords: ATPG; LOW POWER; DELAY TESTING; PATH DELAY FAULTS; STABILITY FUNCTIONS

Document Type: Research article

DOI: http://dx.doi.org/10.1166/jolpe.2005.019

Publication date: 2005-08-01

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The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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