A 1 V–270 W–2 GHz CMOS Synchronized Ring Oscillator Based Prescaler

Authors: Mazouffre, Olivier; Lapuyade, Hervé; Bégueret, Jean-Baptiste; Cathelin, Andreia; Belot, Didier; Deval, Yann

Source: Journal of Low Power Electronics, Volume 1, Number 2, August 2005 , pp. 153-160(8)

Publisher: American Scientific Publishers

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Abstract:

This paper deals with the design and the experimental measurements of a 2 GHz divide-by-4 prescaler for digital cordless and cellular telephone applications in the 1.7 GHz to 2.2 GHz band. We also present the theoretical study of latch-based low-power divider class, used for this divider. The presented circuit is implemented in the CMOS part of the 0.25 m BiCMOS SiGe process from STMicroelectronics. It uses a Synchronized Ring Oscillator architecture based on NMOS pseudo differential latches. The usual latch clock transistors are replaced by the use of the body effect to allow 1 V and under operation. The prescaler draws 270 A from a 1 V power supply, its operating frequency range is from 1.4 GHz to 2.2 GHz and its efficiency is about 8 GHz/mW.

Keywords: PRESCALER; FREQUENCY DIVIDER; LOW-POWER; LOW-VOLTAGE; 2 GHZ; CMOS

Document Type: Research article

DOI: 10.1166/jolpe.2005.016

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