Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing

Authors: Girard, Patrick; Bonhomme, Yannick

Source: Journal of Low Power Electronics, Volume 1, Number 1, April 2005 , pp. 85-95(11)

Publisher: American Scientific Publishers

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Abstract:

Scan architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows design of power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows reducing average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.

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Keywords: DFT; LOW POWER TESTING; SCAN TESTING; SCAN CHAIN DESIGN; SCAN CELL ORDERING

Document Type: Research article

DOI: http://dx.doi.org/10.1166/jolpe.2005.004

Publication date: 2005-04-01

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The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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