Selective Clock-Gating for Low-Power Synchronous Counters

Authors: Parra, Pilar; Acosta, Antonio J.; Jiménez, Raúl; Valencia, Manuel

Source: Journal of Low Power Electronics, Volume 1, Number 1, April 2005 , pp. 11-19(9)

Publisher: American Scientific Publishers

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Abstract:

With current technologies and applications, dynamic power reduction is of great technological interest. The objective of this paper is to explore the applicability of clock gating techniques to counters in order to reduce the power consumption as well as to compare different power figures in counting structures. Counters are widely used in current VLSI digital circuits, and optimized low-power versions of them are of important concern. Different ways of applying clock gating are considered: clock gating on independent bits and clock gating on groups of bits with different synchronization schemes. The correct selection of bits where clock gating is applied and the suitable composition of groups of bits are essential but are not straightforward when applying this technique. We have found that some specific groupings of bits are the best options when applying clock gating to reduce power consumption.

Keywords: LOW-POWER COUNTERS; CLOCK GATING; CMOS VLSI; DYNAMIC POWER CONSUMPTION AND OPTIMIZATION; DIGITAL ELECTRONICS

Document Type: Research article

DOI: 10.1166/jolpe.2005.003

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