Abstract:

This paper presents a new methodology allowing to compare several architectures (or micro- architectures) performing the same function and to select the one presenting the smallest total power consumption under fixed supply voltage (Vdd), threshold voltage (Vth) and frequency (f) constraints. The smallest total power consumption, which is closely related to the architecture, results clearly from a tradeoff between static and dynamic power. Static power reduction leads to select architectures with a small number of cells and not with a small number of transitions, as it was the case when only dynamic power reduction was targeted. As an example, this methodology is applied to the selection of the lowest power consuming architecture among a set of eleven 16 bit multipliers.

Keywords: ARCHITECTURE; DYNAMIC CONSUMPTION; LOW POWER; STATIC CONSUMPTION; MULTIPLIER

Document Type: Research article

DOI: 10.1166/jolpe.2005.006