Impact of Gate Engineering on Gate Leakage Behavior of Nano Scale MOSFETs with High-k Dielectrics
This paper discusses the gate leakage current characteristics based on gate tunnel model for different device structure having high-k dielectric as a gate dielectric and/or a spacer. In this study, a device structures are characterized to reduce the gate leakage current based on gate dielectric and the spacer structures. Several structures were also studied for other electrical performance parameters like on current, off current, drain induced barrier lowering (DIBL), subthreshhold slope(SS). The device structure in which the high-k dielectric extends to the bottom of the oxide spacers showed the smallest gate leakage current while the device structure in which gate dielectric is of high-k material and spacer is of silicon dioxide showed the best DIBL, SS, on current and off current characteristics.
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Document Type: Research Article
Publication date: 2010-12-01
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- Journal of Nanoelectronics and Optoelectronics (JNO) is an international and cross-disciplinary peer reviewed journal to consolidate emerging experimental and theoretical research activities in the areas of nanoscale electronic and optoelectronic materials and devices into a single and unique reference source. JNO aims to facilitate the dissemination of interdisciplinary research results in the inter-related and converging fields of nanoelectronics and optoelectronics.
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