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Modeling Based Design of Graphene Heat Spreaders and Interconnects in 3-D Integrated Circuits

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Abstract:

Computer simulation tools are used to study the feasibility of graphene's applications for thermal management of electronic circuits. We simulated heat propagation in generic 3-D chips built on silicon-on-insulator substrates. Graphene and few-layer graphene were considered to be incorporated within the chips as heat spreaders in order to utilize graphene's extremely high thermal conductivity. They can simultaneously play a role of interconnects. The heat propagation equations were solved numerically using the finite element analysis method. We observed that the incorporation of graphene and few layer graphene with proper heat sinks substantially lowered the temperature of circuits. The maximum temperature within the chip was studied as a function of thermal conductivity of graphene, thickness of few-layer graphene and bonding layer thickness. The simulation results are important for development of the high-heat-flux thermal management approach for semiconductor devices.

Keywords: 3-D CHIP; GRAPHENE; GRAPHENE HEAT SPREADERS; SIMULATION; THERMAL MANAGEMENT

Document Type: Research Article

DOI: https://doi.org/10.1166/jno.2010.1110

Publication date: 2010-12-01

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  • Journal of Nanoelectronics and Optoelectronics (JNO) is an international and cross-disciplinary peer reviewed journal to consolidate emerging experimental and theoretical research activities in the areas of nanoscale electronic and optoelectronic materials and devices into a single and unique reference source. JNO aims to facilitate the dissemination of interdisciplinary research results in the inter-related and converging fields of nanoelectronics and optoelectronics.
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