An Exploratory Design Study of a 16 × 16 Static Random Access Memory Using Silicon Nanowire Transistors

Authors: Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

Source: Journal of Nanoelectronics and Optoelectronics, Volume 2, Number 3, December 2007 , pp. 294-303(10)

Publisher: American Scientific Publishers

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Abstract:

This study presents a nanometer-scale 16 × 16 Static Random Access Memory (SRAM) design using vertical, undoped, dual metal work function silicon nanowire transistors. The design cycle starts with determining individual metal gate work function of each N and P-channel Metal Oxide Semiconductor transistor to produce a 300 mV threshold voltage. Wire radius and effective channel length are both varied to find a common body geometry that minimizes static and dynamic power dissipations while maximizing ON current for both N and P-channel transistors. Once the optimal device dimensions are defined, a 16 × 16 SRAM is built; its transient performance, power dissipation and layout area are measured. Post-layout simulation results indicate that the worst-case read and write access times of the SRAM are 133 ps and 98 ps, respectively; its power dissipation is 331 μW during a read and 251 μW during a write operation at 500 MHz. The SRAM layout occupies approximately 16 μm2.
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  • Journal of Nanoelectronics and Optoelectronics (JNO) is an international and cross-disciplinary peer reviewed journal to consolidate emerging experimental and theoretical research activities in the areas of nanoscale electronic and optoelectronic materials and devices into a single and unique reference source. JNO aims to facilitate the dissemination of interdisciplinary research results in the inter-related and converging fields of nanoelectronics and optoelectronics.
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