Modeling and Simulation of the Nanoscale Triple-Gate Ultra-Thin Body MOS Devices
Abstract:Novel design architecture for nanoscale MOS based devices with very low leakage current has been presented in this paper. The new device is termed as "Parallel Connected Hetero Material Double Gate (PCHEM-DG)" MOSFET. A full two-dimensional numerical analysis has been presented to predict the device physics and its output characteristics. Various leakage current components have been discussed and their variations with respect to bias and device parameters are presented. The results have been compared and contrasted with standard device simulator such as MINIMOS 6.0 for the purpose of validation of the results. A dramatic increase of the gate leakage and Band-to-Band Tunneling (BTBT) leakage in nanoscaled devices drastically increases total leakage power in a logic circuit. This proposed device is expected to reduce the power dissipation. This work provides a simple and intuitive method for lowering of leakage currents which can be very helpful for designing future low power nanoelectronic devices and circuits.
Document Type: Research Article
Publication date: 2006-08-01
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- Journal of Nanoelectronics and Optoelectronics (JNO) is an international and cross-disciplinary peer reviewed journal to consolidate emerging experimental and theoretical research activities in the areas of nanoscale electronic and optoelectronic materials and devices into a single and unique reference source. JNO aims to facilitate the dissemination of interdisciplinary research results in the inter-related and converging fields of nanoelectronics and optoelectronics.
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