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Impact of Strain Engineering on Nanoscale Strained III–V PMOSFETs

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Stress distributions in the strained InGaAs PMOSFET with source/drain (S/D) stressors for various lengths and widths were studied with 3D stress simulations. The resulting mobility improvement was analyzed. Compressive stress along the transport direction was found to dominate the hole mobility improvement for the wide width devices. Stress along the vertical direction perpendicular to the gate oxide was found to affect the mobility the least, while stress along the width direction enhanced in the middle wide width region. The impact of channel width and length on performance improvements such as the mobility gain was analyzed using the Kubo-Greenwood formalism accounting for nonpolar hole-phonon scattering (acoustic and optical), surface roughness scattering, polar phonon scattering, alloy scattering and remote phonon scattering. The novelty of this paper is studying the impact of channel width and length on the performance of InGaAs PMOSFET such as mobility and exploring physical insight for scaling the future III–V CMOS devices.
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Document Type: Research Article

Publication date: 2012-07-01

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  • Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.
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