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Electrical Stress Effect on the Leakage Current of Metal-Induced Laterally Crystallized p-Channel Poly-Si TFTs

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A p-type polycrystalline silicon thin-film transistor (TFT) was fabricated using the metal-induced lateral crystallization (MILC) technique at 550 °C. To reduce the leakage current in the MILC TFT, electrical stress (ES), newly developed in this work, was applied prior to the ID VG measurements. It was found that ES is effective only when the TFT is under off-state. The stress gate voltage is related to the leakage current at high gate voltages and the electric field between the source and the drain to the leakage current at low gate voltages. The leakage current of the MILC TFT could be lowered to 10−11 A for width/length ratios of 1/2 measured at the drain voltage of 3 V. A new plausible model has been suggested to explain the ES effect on the leakage current behavior in low-temperature polycrystalline silicon TFTs.

Document Type: Research Article


Publication date: 2012-04-01

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  • Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.
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