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Through silicon via (TSV) technology is becoming a mainstream method of building 3-dimensional integrated circuits (3D IC). In particular, TSV Cu CMP is a critical process to remove excess Cu and makes a planar surface which requires a removal rate higher than 5 μm/min and
a dishing lower than 0.3 μm. This paper focuses on the development of a new self-alignment method using dimples on the TSV Cu back surface. We tried to find an application potential of a bump-dimple structure for self alignment using a pretest tool of a solder ball array structure.
Chemical-mechanical planarization (CMP) aided dimple etching is carefully studied as a key solution for deep and uniform dimple formation. The experiment shows that CMP is an excellent process to generate a clean oxide surface and a clear dishing on the Cu TSV, resulting in a seed for etching.
Finally, etching realizes a uniform dimple depth of 7 μm to 9 μm in spite of changes of via diameter from 10 μm to 50 μm after only 15 sec etching.
Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.