Charge Trapping Devices Using a Bilayer Oxide Structure

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This experiment is the first exploration of use of charge traps in the bulk of deposited top oxide and at the interface between thermal oxide and deposited top oxide. We report the operational characteristics of SiO2/SiO2 device structures with 0.5 μm gate width and length. Low power operations are achieved through very thin gate stacks of 3 nm of thermally grown oxide and 7 nm of deposited oxide. However, narrow memory windows have been acquired comparing with conventional silicon–oxide–nitride–oxide–silicon (SONOS) memory cells due to a low trap density at the interface between a grown oxide and a deposited oxide. Additionally, the electric field between the channel and the charge is determined by solving 1D Poisson equation at a given write voltage, then total tunneling current density is calculated to make a program modeling for charge trapping devices. Tunneling/trapping simulation based on Fowler-Nordheim (F-N) tunneling performed and it fits the programming curves well. The memory window is almost constant after 100,000 cycles, and the retention characteristics are deteriorated rapidly.


Document Type: Research Article


Publication date: January 1, 2012

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  • Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.
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