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Effects of Device and Peripheral Parameters on Transconductance of Silicon Nanowire Transistors

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Abstract:

This paper presents a general analysis over the transconductance function in silicon nanowire transistors (SNWTs). The transconductance function in SNWTs has been well-discussed and the relation between this function and the physical and peripheral parameters of the SNWT has been precisely investigated. The transconductance expression has been derived as a function of device parameters (e.g., oxide capacitor, electron effective-mass) and applied voltage biases, which helps to understand the essential physics of one-dimensional (1D) nanowire FETs and to interpret numerical simulation results. These simulations demonstrate the transconductance formulation as a function of environmental temperature, voltage biases and oxide layer thickness.

Keywords: DEVICE PARAMETERS; NUMERICAL SIMULATION; SILICON NANOWIRE TRANSISTOR; TRANSCONDUCTANCE

Document Type: Research Article

DOI: http://dx.doi.org/10.1166/jnn.2011.3996

Publication date: December 1, 2011

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  • Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.
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