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Reduced Distribution of Threshold Voltage Shift in Double Layer NiSi2 Nanocrystals for Nano-Floating Gate Memory Applications

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We report on the fabrication and capacitance–voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (±2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 × 1012 cm−2. The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C–V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.
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Keywords: DOUBLE LAYER; NANO FLOATING GATE MEMORY; NANOCRYSTALS; NISI2

Document Type: Research Article

Publication date: 2011-12-01

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  • Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.
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