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Fabrication and Characterization of Twin Poly-Si Thin Film Transistors EEPROM with a Nitride Charge Trapping Layer

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This study investigates the characteristics of the planar twin poly-Si thin film transistor (TFT) EEPROM that utilizes a nitride (Si3N4) charge trapping layer. A comparison is made of two devices with different gate dielectrics, one a 16 nm-thick oxide (SiO2) layer for O-structure and the other 5 nm/10 nm-thick oxide/nitride layers for O/N-structure. Incorporating a nitride charge trapping layer and reducing the tunneling oxide thickness enable the O/N-structure EEPROM to enhance the program/erase (P/E) efficiency. Additionally, EEPROM formed with the tri-gate nanowires (NWs) structure can further enhance P/E efficiency and a large memory window because of its high electric field across the tunneling oxide. Reliability results indicated that, since the nitride layer contains discrete traps, the memory window can be maintained 2.2 V after 104 P/E cycles. For retention, the memory window can be maintained 1.9 V, and 30% charge loss for ten years of data storage. This investigation indicates that its possibility in future system-on-panel (SOP) of thin-film transistor liquid crystal display (TFTLCD) and 3-D stacked high-density Flash memory applications.
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Document Type: Research Article

Publication date: 2011-12-01

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  • Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.
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