Impact of Drift Gap, N-Layer, and Deep N+ Sinker on Breakdown Voltage and Saturation Current of Lateral Double-Diffused Metal Oxide Semiconductor Transistor
In this paper, we discuss on the optimal design of a High-Side n-channel Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOSFET) whose breakdown voltage is over 100 V with 0.35 μm Bipolar-CMOS-DMOS (BCD) process. The proposed nLDMOSFET has been fabricated and tested in order to confirm the features of a deep N+ sinker and a gap of between the drift region (DEEP N-WELL) and the center of the source. The surface is implanted by the N-layer for high breakdown voltage and simultaneously the low specific on-resistance. The computer simulation of the proposed High-Side LDMOS exhibits BVdss of 115 V and Ron, sp of as low as 2.20 mΩ·cm2, which is consistent with the experimental results.
No Reference information available - sign in for access.
No Citation information available - sign in for access.
No Supplementary Data.
Document Type: Research Article
Publication date: 2011-08-01
More about this publication?
- Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.
- Editorial Board
- Information for Authors
- Subscribe to this Title
- Terms & Conditions
- Ingenta Connect is not responsible for the content or availability of external websites