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Bias Stress Effects on Different Dielectric Surfaces of Pentacene Thin-Film Transistors

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In this paper, it was demonstrated that pentacene thin-film transistors (TFTs) were fabricated with an organic adhesion layer between an organic semiconductor and a gate insulator. In order to form polymeric film as an adhesion layer, a vapor deposition polymerization (VDP) process was introduced to substitute for the usual spin-coating process. Field effect mobility, threshold voltage, and on/off current ratio in pentacene TFTs with a 15 nm thick organic adhesion layer were about 0.4 cm2/Vs, −1 V, and 106, respectively. We also demonstrated that threshold voltage strongly depends on the stress time when a gate voltage has been applied for bias stress test. We suggest that a polyimide adhesion layer fabricated by the VDP method can be applied to realize organic TFTs with long-term stability because of lower threshold voltage shifts due to reduced charge trapping at the interface between the pentacene semiconductor and the polyimide layer.


Document Type: Research Article

DOI: http://dx.doi.org/10.1166/jnn.2011.3651

Publication date: May 1, 2011

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  • Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.
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