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Variations in the Memory Capability of Nonvolatile Memory Devices Fabricated Using Hybrid Composites of InP Nanoparticles and a Polystyrene Layer Due to the Scale-Down

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Abstract:

InP nanoparticles were formed using a solution method, and the InP nanoparticles that were embedded in a polystyrene (PS) layer were formed using the spin-coating method. The transmission electron microscopy images showed that the InP nanoparticles were randomly distributed in the PS layer. The measured capacitance–voltage (CV) of the Al/InP nanoparticles embedded in the PS layer/PS/p-Si(100) device at 300 K showed a clockwise hysteresis of the CV curve. Based on the CV results, the origin of variations in the memory storage of nonvolatile memory devices that were fabricated using InP nanoparticles embedded in a PS layer due to the scale-down was described.

Keywords: INP NANOPARTICLES; NONVOLATILE MEMORY DEVICES; POLYSTYRENE; SCALE-DOWN; SOLUTION METHOD

Document Type: Research Article

DOI: https://doi.org/10.1166/jnn.2011.3172

Publication date: 2011-01-01

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  • Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.
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