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A New Cost Effective Method of Planarisation for Multiple Metal Layers in the Sub-100 nm-Region

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The availability of multiple metal layers has become essential for high-density layouts and economic chip size. The presented paper describes an efficient and low-cost alternative to Chemical-Mechanical-Polishing (CMP). The method uses an auxiliary wafer as a sort of plunger. Starting with a preprocessed wafer, for example from a Complementary-Metal-Oxide-Semiconductor (CMOS) technology, a spin-on glass is applied before the deposition of the first metal layer. Afterwards a second silicon wafer will be covered homogeneously with photo resist and subsequentially coated with aluminum or titanium. This wafer serves as a plunger, while the metal layer protects the photo resist against impression. Whilst the plunger is pressed down on the spin-on glass, the first wafer is cooled down bonding the two wafers together. Separation of the wafers is accomplished by removing the photo resist layer. After the separation step any remaining photo resist as well as the aluminum layer are removed by etching. This process results in a planar surface which is optimally suited for the deposition and structuring of further metal layers which lead to more freedom concerning the complex interconnects in modern analog and digital circuits.
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Document Type: Research Article

Publication date: 2010-09-01

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  • Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.
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