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Supply Voltage Minimization Techniques for SRAM Leakage Reduction

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In low power design, it is difficult to suppress leakage current. In memory, leakage power reduction during data-retention in SRAM standby is often addressed by reducing the supply voltage. Each SRAM cell has a minimum supply voltage parameter called the data-retention voltage (DRV), above which the stored bit can be retained reliably. As supply voltage is lowered, leakage power reduces. This paper models the DRV of SRAM module, and analyzes the SRAM cell stability when V DD approaches DRV. DRV of the 4 KB SRAM module in a 0.13 mm technology ranges between 60 and 390 mv.
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Keywords: DRV; LEAKAGE CURRENT; LOW POWER; SRAM

Document Type: Research Article

Publication date: 2012-08-01

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  • Journal of Computational and Theoretical Nanoscience is an international peer-reviewed journal with a wide-ranging coverage, consolidates research activities in all aspects of computational and theoretical nanoscience into a single reference source. This journal offers scientists and engineers peer-reviewed research papers in all aspects of computational and theoretical nanoscience and nanotechnology in chemistry, physics, materials science, engineering and biology to publish original full papers and timely state-of-the-art reviews and short communications encompassing the fundamental and applied research.
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