Gate Leakage Power Analysis for a Nanoscale N-MOSFET
As the CMOS devices are scaled down to the regime of deep-sub micrometer and below in order to take the advantage of higher density, high speed and lower cost, power leakage (i.e., dissipation) through gate becomes important because of continued reduction of gate dielectric at nanoscale regime. Consequently, accurate analysis of gate power dissipation is very important especially in context of low power application. In this paper, a method is devised in which gate leakage power is estimated by multiplying the gate voltage (Vg = 0.6 V) and gate leakage current. First of all, analytical model of gate leakage current is developed and hence gate leakage power is calculated. Our analytical model of gate leakage current for sub50-nm generation MOSFET includes the fringing field effect in the gate sidewall. This effect is considered for the first time. The calculated gate current is verified with the experimentally measured data. It is observed that neglecting the fringing field effect in the gate sidewall may lead to large error in the calculated gate tunneling current and hence power. The results provide a guideline to the severity of this effect from the point of view of standby power consumption. It is found that temperature and substrate bias has almost negligible effect on gate leakage power.
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Document Type: Research Article
Publication date: 2008-11-01
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- Journal of Computational and Theoretical Nanoscience is an international peer-reviewed journal with a wide-ranging coverage, consolidates research activities in all aspects of computational and theoretical nanoscience into a single reference source. This journal offers scientists and engineers peer-reviewed research papers in all aspects of computational and theoretical nanoscience and nanotechnology in chemistry, physics, materials science, engineering and biology to publish original full papers and timely state-of-the-art reviews and short communications encompassing the fundamental and applied research.
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