Application-Driven Simulation of Nanoscaled CMOS Transistors and Circuits
Problems in the application-driven simulation of nanoscaled CMOS transistors and circuits are addressed in this paper. First, major physical effects determining the transistor performance at nanoscale gate lengths are considered, then a verification of the simulation models is shown. As example, a comparison of the scaling properties of three MOS transistor architectures along the ITRS guide lines and a simulation of the dynamic performance of an SRAM circuit are considered. A newtypical feature of nanoscaled MOS transistors is that the transistor performance is influenced by several additional physical effects and the effects which have been considered before as small, extrinsic, or parasitic are nowdetermining the transistor performance. At nanoscale, mechanical stress, contact resistances, and parasitic capacitances have important influences on MOS transistor performance. These parasitic factors determining the performance of the integrated circuits based on nanoscaled transistors depend on the processing technology, device architecture, and in certain cases also on circuit architecture.
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Document Type: Research Article
Publication date: 2008-06-01
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- Journal of Computational and Theoretical Nanoscience is an international peer-reviewed journal with a wide-ranging coverage, consolidates research activities in all aspects of computational and theoretical nanoscience into a single reference source. This journal offers scientists and engineers peer-reviewed research papers in all aspects of computational and theoretical nanoscience and nanotechnology in chemistry, physics, materials science, engineering and biology to publish original full papers and timely state-of-the-art reviews and short communications encompassing the fundamental and applied research.
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