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Spatial Interconnect Analysis for Predictable Nanotechnologies

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This paper addresses the interconnect problem for the representation of logic networks in spatial dimensions. Interest in spatial interconnects is motivated by the advent of nanotechnologies and by consequent attempts to evaluate and explore the appropriate nanoscale architectures. It have been shown in our previous study that a 3D logic network with target topology can be designed by replacing each elementary logic block in a network by its 3D model. In this paper, we study the problem of the partitioning of these 3D blocks with respect to the constraints of logic function interconnects and hypercube-like topology. We found that decomposition techniques provide flexibility in choosing switching functions for assembling the decomposed sub-networks.


Document Type: Research Article


Publication date: 2008-01-01

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  • Journal of Computational and Theoretical Nanoscience is an international peer-reviewed journal with a wide-ranging coverage, consolidates research activities in all aspects of computational and theoretical nanoscience into a single reference source. This journal offers scientists and engineers peer-reviewed research papers in all aspects of computational and theoretical nanoscience and nanotechnology in chemistry, physics, materials science, engineering and biology to publish original full papers and timely state-of-the-art reviews and short communications encompassing the fundamental and applied research.
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