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Spatial Systolic Arrays Design for Predictable Nanotechnologies

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Abstract:

Systolic arrays are considered to be one of the prime candidate architectures for nanoscale designs. Interest in systolic arrays has been recently renewed because of the advent of nanotechnology and resulting attempts to evaluate and explore the appropriate nanoscale architectures. The pipelined logic style and functional flexibility of the systolic arrays is well-suited to the ultimate scalability of nanostructures, and the locality of its connections, this is a method of avoiding long range interconnection constitutes. In this paper, we introduce a systematic method for designing the systolic arrays, emphasizing on the problem of computing switching functions in the form of Reed-Muller, arithmetic, and Walsh expressions. The event-driven techniques related to these expressions are introduced as well. These transforms are needed for the techniques of data manipulation at various levels of circuit design. Our approach to the design of spatial systolic arrays is based on the tree-like systolic arrays which are embedded into spatial structures. In this way, a spatial parallelism at global and local levels is utilized.

Keywords: LOGIC DESIGN; NANODEVICES; SYSTOLIC ARRAYS

Document Type: Research Article

DOI: https://doi.org/10.1166/jctn.2007.2330

Publication date: 2007-05-01

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  • Journal of Computational and Theoretical Nanoscience is an international peer-reviewed journal with a wide-ranging coverage, consolidates research activities in all aspects of computational and theoretical nanoscience into a single reference source. This journal offers scientists and engineers peer-reviewed research papers in all aspects of computational and theoretical nanoscience and nanotechnology in chemistry, physics, materials science, engineering and biology to publish original full papers and timely state-of-the-art reviews and short communications encompassing the fundamental and applied research.
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