Logic Design of Computational Nanostructures
From a nano-fabrication viewpoint, computing networks can be designed based on multiterminal nanoelectronic devices, and can be created using self-assembly and synthesis of massively locallyconnected logic elements. This paper draws connections to contemporary approaches to computer hardware design. However, it abstracts from the traditional orientation of very large scale integration (VLSI) technology and ultra large scale integration (ULSI) technology. We revised and apply the state-of-the-art design techniques to the nanoscale domain. Because today's nanodevices are weak and sensitive, they are not suited to conventional logic gate architectures, which require robust devices. The focus of investigation is the data structures that satisfy the criteria of massive parallel processing, homogeneity, and fault tolerance. The focus is hypercube and hypercube-like structures, synthesis of spatial data structures, and assembly of topological models. The key features that distinguish our study from others include the central role of topological models (embedding in hypercubes, assembling the topology), revised techniques of advanced logic design, and stochastic computing techniques.
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Document Type: Review Article
Publication date: 2007-05-01
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- Journal of Computational and Theoretical Nanoscience is an international peer-reviewed journal with a wide-ranging coverage, consolidates research activities in all aspects of computational and theoretical nanoscience into a single reference source. This journal offers scientists and engineers peer-reviewed research papers in all aspects of computational and theoretical nanoscience and nanotechnology in chemistry, physics, materials science, engineering and biology to publish original full papers and timely state-of-the-art reviews and short communications encompassing the fundamental and applied research.
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