Authors: Gehring, Andreas; Selberherr, Siegfried

Source: Journal of Computational and Theoretical Nanoscience, Volume 2, Number 1, March 2005 , pp. 26-44(19)

Publisher: American Scientific Publishers

Abstract:

We describe a set of models suitable for the two- and three-dimensional simulation of tunneling in logic and non-volatile MOS devices. The crucial modeling topics are comprehensively discussed. This comprises the modeling of the energy distribution function in the channel to account for hot-carrier tunneling, the calculation of the transmission coefficient of single and layered dielectrics, the influence of quasi-bound states in the inversion layer, the modeling of static and transient defect-assisted tunneling, and the modeling of dielectric degradation and breakdown. We propose a set of models to link the gate leakage to the creation of traps in the dielectric layer, the threshold voltage shift, and eventual dielectric breakdown. The simulation results are compared to commonly used compact models and measurements of logic and non-volatile memory devices.

Keywords: SEMICONDUCTOR DEVICE SIMULATION; MOS TUNNELING; ENERGY DISTRIBUTION FUNCTION; HIGH-K DIELECTRICS; TRANSMITTING-BOUNDARY; TRANSFER-MATRIX; TRAP-ASSISTED TUNNELING

Document Type: Review article

DOI: http://dx.doi.org/10.1166/jctn.2005.002

Publication date: 2005-03-01

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• Journal of Computational and Theoretical Nanoscience is an international peer-reviewed journal with a wide-ranging coverage, consolidates research activities in all aspects of computational and theoretical nanoscience into a single reference source. This journal offers scientists and engineers peer-reviewed research papers in all aspects of computational and theoretical nanoscience and nanotechnology in chemistry, physics, materials science, engineering and biology to publish original full papers and timely state-of-the-art reviews and short communications encompassing the fundamental and applied research.
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