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Systematic Methods to Evaluate Fault-Tolerant Behavior of Nanoscale Circuits

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Abstract:

This paper focuses on the investigation of efficient methods to evaluate circuit fault-tolerance. We propose a fault-tolerance evaluation method based on the Belief Propagation (BP) algorithm. Compared with existing approaches, our algorithm is more efficient in terms of memory requirements and CPU time. The algorithm can easily run on multiple CPUs to achieve parallel processing, and thus further reducing memory cost and processing time. The significance of this research is that the proposed algorithm can be used for developing computer-aided nanoscale simulation tools to systemically evaluate circuit fault-tolerant behavior. This knowledge, in turn, can help build more robust nanocircuits.

Keywords: COMPUTER-AIDED CIRCUIT SIMULATION; FAULT-TOLERANT NANOSCALE CIRCUITS; PROBABILISTIC-BASED DESIGN

Document Type: Research Article

DOI: http://dx.doi.org/10.1166/asl.2011.1973

Publication date: November 1, 2011

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  • ADVANCED SCIENCE LETTERS is an international peer-reviewed journal with a very wide-ranging coverage, consolidates research activities in all areas of (1) Physical Sciences, (2) Biological Sciences, (3) Mathematical Sciences, (4) Engineering, (5) Computer and Information Sciences, and (6) Geosciences to publish original short communications, full research papers and timely brief (mini) reviews with authors photo and biography encompassing the basic and applied research and current developments in educational aspects of these scientific areas.
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