A Power Efficient Binary Multiplier Circuit with Overflow Detection Using Single Spin Logic Circuit: Design and Implementation

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Abstract:

The basic needs of modern Electronic industry are low power consumption high operating speed and high integration density equipments. As a consequence, the search for new principle of operation of the small size and low power consuming devices is becoming more and more important. Recent advances in controlling quantum 'spin' effect have broaden the path for the newly emerging field, called 'spin based electronic' or 'spintronics.' It is not the electronic charge but the electrons spin that carry information and they offer opportunities for a new generation of novel devices that are extremely fast. In spin based electronics information is injected, stored or manipulated with spin degree of freedom. In the present work, several multipliers (with overflow detection capability) like unsigned array multipliers, unsigned tree multipliers and two's complement multipliers are realized employing single spin logic circuit to save area and time.

Document Type: Research Article

DOI: http://dx.doi.org/10.1166/asl.2009.1071

Publication date: September 1, 2009

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  • ADVANCED SCIENCE LETTERS is an international peer-reviewed journal with a very wide-ranging coverage, consolidates research activities in all areas of (1) Physical Sciences, (2) Biological Sciences, (3) Mathematical Sciences, (4) Engineering, (5) Computer and Information Sciences, and (6) Geosciences to publish original short communications, full research papers and timely brief (mini) reviews with authors photo and biography encompassing the basic and applied research and current developments in educational aspects of these scientific areas.
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