Task Selection for the Multiscalar Architecture

Authors: Vijaykumar T.N.¹; Sohi G.S.²

Source: Journal of Parallel and Distributed Computing, Volume 58, Number 2, August 1999 , pp. 132-158(27)

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Abstract:

The multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential programs without impeding improvements in clock speeds. The main goal of this paper is to understand the key implications of the architectural features of distributed processor organization and task-level speculation for compiler task selection from the point of view of performance. We identify the fundamental performance issues to be: control flow speculation, data communication, data dependence speculation, load imbalance, and task overhead. We show that these issues are intimately related to a few key characteristics of tasks: task size, intertask control flow, and intertask data dependence. We describe compiler heuristics to select tasks with favorable characteristics. We report experimental results to show that the heuristics are successful in boosting overall performance by establishing larger ILP windows. We also present a breakdown of execution times to show that register wait, load imbalance, control flow squash, and conventional pipeline losses are significant for almost all the SPEC95 benchmarks. Copyright 1999 Academic Press.

Language: English

Document Type: Research article

Affiliations: 1: School of Electrical & Computer Engineering, Purdue University, EE Building, West Lafayette, Indiana, 47907 2: Computer Sciences Department, University of Wisconsin-Madison, West Dayton Street, Madison, Wisconsin, 53706

Publication date: 1999-08-01