A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip

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A dynamically reconfigurable bit-serial systolic array implemented in 1.2-mum double-metal P-well CMOS is described. This processor array is proposed as the central computational unit in the Reconfigurable Systolic Array (RSA) neuro-computer and performance estimates suggest that a 64 IC system (containing a total of 1024 usable processors) can achieve a learning rate of 1134 MCUPS on the NETtalk problem. The architecture employs reconfiguration techniques for both fault-tolerance and functionality, and allows a number of neural network models (in both the recall and learning phases) from associative memory networks, supervised networks, and unsupervised networks to be supported.

Document Type: Research Article

Affiliations: 1: Quality Semiconductor Australia, Homebush, New South Wales, 2140, Australia 2: Faculty of Informatics, University of Wollongong, Wollongong, New South Wales, 2522, Australia

Publication date: July 1, 1997

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